CHAMPAIGN, ILLOCAL TIME /
// COMPUTER ENGINEERING @ UIUC
CPU architecture
& RTL design.
I’m Constantine, a full-time computer engineering student at UIUC. Most of my work is CPU architecture and RTL design and verification.
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FIG. 001PROCESSOR ASSEMBLYCONCEPT MODEL / NOT TO SCALE
DRAG TO ORBIT · + / − TO ZOOM
01 — INTRODUCTIONPROJECTS ↓
RISC-V assemblerEncode an instruction or inspect its bits.Open toolClose tool+
R-type
HEX
UNSIGNED
SIGNED
31 / MSBLSB / 0
Type an RV32IM instruction, or toggle a bit to decode its value. Register names and ABI aliases are supported.